Memory Layout Engineer
Mirafra Technologies
2 - 5 years
Bengaluru
Posted: 10/01/2026
Job Description
Hiring: SRAM Memory IP Layout Engineer
We are looking for an experienced SRAM Memory IP Layout Engineer who can independently handle memory layout development.
Key Responsibilities:
SRAM Memory IP layout development
Calibre DRC/LVS verification
Leaf-cell development for SAM blocks
Requirements:
210 years of relevant experience
Strong hands-on experience with Calibre DRC/LVS
Ability to work independently on layout activities
Notice Period: 090 days
Qualifications:
B.Tech / B.E / M.Tech / M.E
Interested candidates can reach out or share their profiles.
Krithika M
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