Memory Circuit Design Verification Engineer

Memory Circuit Design Verification Engineer, will contribute to the verification of advanced DRAM and HBM memory products.

Work closely with a dynamic team to ensure timely delivery of functionally correct designs, collaborating with global teams and leveraging state-of-the-art verification methodologies.

Key Responsibilities

Perform FastSpice-based verification (Primesim, FineSim, SpectreFx) for DRAM critical timings and full-chip analog simulation across PVTs and speed grades.

Develop, maintain, and execute System Verilog/UVM-based testbenches and verification environments for full-chip validation.

Analyze and debug pre-silicon full-chip designs, focusing on timing closure and functional coverage.

Collaborate and communicate effectively with cross-geo teams (e.g., US) to align verification flows and share technical insights.

Document verification results, report issues, and contribute to continuous improvement of verification methodologies.

Must-Have Skills

Hands-on experience with Fast Spice simulators for analog and mixed-signal verification.

Proficiency in System Verilog/UVM-based verification methodology.

Strong understanding of DRAM memory architecture and timing analysis.

Secondary Skills

Scripting skills in Python or Tcl for automation and regression analysis.

Familiarity with EDA tools such as Virtuoso, FineSim, Hspice, Xcelium, SimVision, WaveView.

Ability to collaborate and communicate effectively with global teams and stakeholders.

Qualifications

Bachelors or masters degree in electrical/Electronic Engineering or related field.

410years of relevant experience in memory verification (DRAM/HBM/SRAM).

Strong problem-solving and debugging skills.

Good written and verbal communication skills.