Leading MNC IT Service - ASIC Verification Lead

Main responsibilities:

* Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams.

* Participate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications.

* Write and perform closely test plans with the logical design team.

* Develop coverage models and verification environments using UVM-SystemVerilog / C ++

* Monitor, analyze and debug simulation errors.

* Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.

* Submit recommendations on tools and methodologies to develop to improve productivity. Mentor junior engineers on how to produce a maintainable and reusable code across projects.

Skills:

* Participated in the successful verification of a complex SoC or ASIC.

* Mastering UVM or equivalent verification methodology.

* Proficient developer of Constraint-Random / Coverage-Driven verification environments in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA)

* Strong knowledge of simulation tools and coverage database visualization tools

* Developed test plans that helped identifying sharp functional defects.

* efficiency in problem solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints

* Experienced in improving processes and methodologies

* Experience in managing tasks for a small team.

Required minimum experience:

* Master/Engineer in Electronics and Communication Engineering.