Lead Verification Engineer

Lead Verification Engineer

Location: Bengaluru, India

Experience: 6+ Years

About the Role

We are looking for a Lead Verification Engineer to drive the verification of next-generation high-speed interconnect technologies including PCIe Gen5/Gen6/Gen7 and CXL. You will work on cutting-edge silicon powering AI, data center, networking, and high-performance computing platforms.

In this role, you will architect and execute complex SystemVerilog/UVM verification environments, collaborate with architecture, design, and validation teams, and ensure first-silicon success of high-performance SoC/IP products.

This is a high-impact opportunity to work on industry-defining connectivity standards used across hyperscale infrastructure.

What Youll Do

• Lead end-to-end verification of complex PCIe / CXL IPs and SoC subsystems.
• Architect scalable SystemVerilog/UVM verification environments.
• Develop advanced testbench components, sequences, monitors, scoreboards, and coverage models.
• Drive functional, protocol, and performance verification for PCIe Gen5/Gen6/Gen7 and CXL protocols.
• Develop constrained-random verification strategies and achieve high coverage closure.
• Work closely with design, architecture, and firmware teams to debug complex issues.
• Analyze and debug failures using simulation, waveform analysis, and protocol analyzers.
• Contribute to verification planning, methodology improvements, and automation frameworks.
• Mentor junior engineers and help scale the verification infrastructure.

Qualifications

• 6+ years of experience in IP/SoC verification.
• Strong expertise in SystemVerilog and UVM-based verification.
• Solid hands-on experience verifying PCIe Gen5/Gen6/Gen7 protocols.
• Good understanding of CXL protocol (CXL.io, CXL.cache, CXL.mem).
• Experience building UVM components, sequences, scoreboards, and coverage models.
• Strong debugging skills using simulation tools and waveform analysis.
• Experience with functional coverage and coverage closure.
• Familiarity with SoC-level verification and subsystem integration.

Preferred Qualifications

• Experience verifying high-speed interfaces such as PCIe, CXL, DDR, Ethernet, or NVMe.
• Experience with VIP integration (PCIe/CXL VIP).
• Knowledge of link training, LTSSM, flow control, and protocol compliance.
• Exposure to emulation or FPGA prototyping environments.
• Scripting experience with Python / Perl / Shell for automation.
• Prior experience leading verification efforts or mentoring engineers.

Why Join Us

• Work on next-generation connectivity technologies (PCIe Gen7 / CXL).
• Build silicon powering AI, cloud, and hyperscale infrastructure.
• Collaborate with world-class silicon architects and verification experts.
• Opportunity to lead complex verification programs with real impact.

About Us:

Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, were committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.

Website

https://www.siliconpatterns.com