Lead Verification Engineer

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Job Description:

Join a team of highly competent ASIC designers involved in design, verification, and implementation of advanced High Speed Interconnect Products for Communications Networks at speeds of 100Gbps+.

Play active role and be a part of the team that defines the verification strategy and the development. In this role you will be working with verification of cutting edge technologies that include features related to FEC, Tx training, CDR, PLL tuning etc.

• Develop and execute coverage-driven verification test plans.
• Develop test suites for full chip and block level verification.
• Develop System Verilog, VMM/UMM test bench environment.
• Leverage your knowledge of constrained assertion based verification.
• Manage the regressions and analyze functional and code coverage metrics to fill the coverage holes.
• Reviewing and critiquing of peers verification plan & env.
• Add automation and scripting wherever applicable in the chip design flow.
• Proactively identifying new methodologies or tools to address an upcoming verification challenges.

Job Requirements

• MSEE/BSEE with 8+ years in chip design verification.
• Experience in planning the verification process and creating realistic schedule estimates.
• Experience in High Level Verification languages: System Verilog is a must.
• Strong experience in high level Object Oriented test bench environments such as UVM or any equivalent.
• Experience in verifying complex verification blocks like PLL calibrations, multi clock, reset domain designs and mixed signal interfaces is a big plus.

• Knowledge of Ethernet and OTN standards and IEEE 802.3 Physical layer clauses like Cl.72, 93, 91 etc. is preferred

•  Excellent knowledge of PCIE protocol - Gen3 and above is a plus
• Deeper understanding of PLLs/CDR concepts/AMS interfaces and networking IP designs are preferred.
• Experience in developing coverage-driven verification test plans
• Experience writing test specifications (plans) and creating directed and random test cases.
• Experience in developing constrained random verification environment
• Experience managing regression analysis
• Experience in reviewing and critiquing of test bench and test plans
• Strong debugging skills of Verilog RTL & test environment is desired
• Able to adopt the use of new techniques and methodologies and promote their use within the project.
• A high level of pro-activity, self-organized and problem solving.
• Experience with assertion based verification is preferred
• Verification experience in SERDES, Ethernet Networking in Verilog is a big plus.
• Experience with scripting languages such as PERL, TCL Unix Scripting is highly desirable

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

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