Roles & Responsibilities:

To train and lead a team of 5 to 8 engineers
Defining and verification of STA constraint for Functional and Test/SCANModes.
Defining PVTs corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates.
Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues.
VASTA timing closure based on chip IR drop.
Knowledge on signal SI analysis and PT-PX flow.

Qualifications

BE/B.Tech/M.Tech with 5 to 8 years.
Project leading knowledge is preferred.
Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations.
Candidate should have strong STA fundamentals.
Has done timing sign-off including timing margin calculations. Independently, hands-on STA lead of projects.
Experience in handling STA of multi-power domain designs & constraint mode merging.
STA flow development, abstraction with bottleneck identification.
Proficient in design margins and SDC constructs. TAT reduction in multi-mode, multi power domain/designs.
Generate timing ECOs for Physical design.
Drive ambitious schedules and enables dependent teams to accomplish.
Interface to design team and PD team and drive TAT reduction for PD.
Has experience in mentoring junior engineers.
Proficient with EDA tools from Synopsys/Cadence.
Excellent analytical & communication skills.
Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone.
Proficient in Tcl and Perl or other scripting relevant language is a plus.

Lead Static Timing Analysis Engineer