Lead - STA Engineer

Lead STA Engineer

Experience: 10+ Years

Location: Bangalore

Job Summary:

We are looking for a highly skilled STA Engineer with 10+ years of experience in timing analysis and closure for complex IP and SoC designs. The candidate will be responsible for driving block-level and full-chip STA sign-off, handling cross-functional interactions, and delivering timing closure for high-performance designs.

Key Responsibilities:

• Drive end-to-end Static Timing Analysis for block and SoC level designs.
• Own timing closure from synthesis to GDSII.
• Perform timing sign-off including:
• MCMM setup and analysis
• OCV/AOCV/POCV
• Crosstalk and noise analysis
• SI-aware timing closure
• Develop and validate timing constraints (SDC).
• Analyze and fix setup, hold, transition, and capacitance violations.
• Work closely with PD, synthesis, DFT, and RTL teams for timing convergence.
• Handle ECO implementation and validation for timing closure.
• Perform gate-level simulation support for timing validation.
• Drive timing methodologies, flow improvements, and automation.
• Mentor junior engineers and review timing sign-off quality.

Required Technical Skills:

• Strong expertise in PrimeTime / Tempus for STA and sign-off.
• Deep understanding of:
• Timing constraints development and debugging
• MCMM timing environments
• Variation modeling (OCV, AOCV, POCV)
• CRPR, useful skew, path-based analysis
• Experience in high-frequency and low-power designs.
• Strong knowledge of clock tree concepts and timing interaction with CTS.
• Understanding of physical design flow and timing-driven implementation.
• Experience with SI analysis and noise-aware timing closure.
• Proficiency in Tcl / Perl / Python scripting for automation.
• Strong debugging and timing analysis skills.

Nice to Have:

• Experience in advanced technology nodes (7nm / 5nm / 3nm)
• Low-power timing verification using UPF/CPF
• MMMC flow setup from scratch
• Exposure to hierarchical STA / full-chip integration
• Formal equivalence check (timing ECO validation)

Soft Skills:

• Ability to lead timing closure for large SoCs.
• Strong analytical and problem-solving skills.
• Excellent stakeholder communication and collaboration.

Education:

• BE / B.Tech / MS in Electronics / Electrical / VLSI or related field.