Lead STA Design Engineer

About Samsung Semiconductor India Research (SSIR)

With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.

As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.

Roles and Responsibilities

Looking for bright ASIC design engineer with excellent analytical and technical skills. This role provides opportunity to participate in the ASIC development, with emphasis in synthesis, timing closure, low power, place and route.

Responsibilities include:

Oversee and mentor a team of STA engineers, ensuring timely project execution for a Chip and Subsystems

Develop constraints, run synthesis, perform low power, timing and equivalence checks and closure

Work closely with RTL designer, physical design, low power teams to optimize performance, area and power

Generate, review and validate design constraints to achieve timing closure of high speed design

Develop floor-planning and CTS guidelines for layout

Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, and work closely with layout engineers to achieve critical high speed path timing closure

Perform in-house quality check before P&R and after P&R

Constraint management tool and Verilog coding experience

Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples

Improve existing process and enhance team work efficiency

Must have BSEE or MSEE in EE with 12+ years of relevant experience in the following areas:

Must be hands-on technical expert

Strong written and oral communication skills

Good understanding of Deep Sub Micron topics and their associated issues

Good Experience in Top/Block DCT/DCG based Synthesis, Equivalence checks

Experience in leading Hard-IP/HardBlocks/SOC timing closure with deep technical knowledge in all

Should be able to comprehend architecture and associated limitations with respect to synthesis and STA perspective and be able to predict the schedule, amount of task and personnel involved

Good experience with functional and test mode constraints and developing IOs and IP constraints, optimization, STA setup with associated automation, cross-talk noise/delay, STA signoff, GCA, VCLP

Good understanding of Low Power Management and experience with its implication on synthesis and STA

Should have ability to develop good understanding of a design and associated IPs

Very good in understanding and defining constraints and critical high speed path timing closure working with BE teams

Perl/Tcl scripting is required

Good understanding of the APR flows is desired

Experience 14 to 20 Years

Qualifications

• B.Tech/B.E/M.Tech/M.E

Disclaimer

Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.