Lead RTL Design Engineer

Lead ASIC RTL Design Engineer

Location: Bangalore, India

Experience: 6+ Years

Education: BS/BE/MS/M.Tech in Electrical Engineering, Electronics, or related field

About the Role

We are looking for a Lead ASIC RTL Design Engineer to architect and implement high-performance digital logic for next-generation mixed-signal and digital ICs in advanced CMOS technologies. In this role, you will design and develop robust RTL for complex ASIC subsystems, particularly focusing on digital control of mixed-signal circuits such as ADCs and PLLs.

You will collaborate closely with analog, verification, and physical design teams to deliver high-quality silicon solutions for cutting-edge semiconductor products.

Key Responsibilities

• Lead the RTL architecture, design, and implementation of complex ASIC subsystems.
• Develop high-quality Verilog RTL for high-performance digital logic, including:
• Finite State Machines (FSMs)
• Arithmetic units (adders, multipliers)
• Complex combinational and sequential logic
• Design and implement digital control logic for mixed-signal systems, including interfaces and control loops for analog blocks such as:
• ADCs
• Digital PLLs
• Mixed-signal control subsystems
• Work closely with analog designers to integrate digital control with analog circuits.
• Develop behavioral models in Verilog, including modeling using wreal constructs for mixed-signal simulation.
• Write comprehensive testbenches for functional verification of RTL blocks.
• Define and implement design constraints for synthesis and timing closure.
• Handle multi-clock domain designs, clock gating, and low-power design considerations.
• Collaborate with verification, physical design, and system teams to ensure design robustness and performance targets.

Required Qualifications

• BS/BE/MS/M.Tech in Electrical Engineering, Electronics, or related discipline.
• 6+ years of experience in high-performance digital or mixed-signal IC design in advanced CMOS processes.
• Strong foundation in digital design concepts for complex ASICs.
• Hands-on experience in Verilog RTL coding for high-performance digital logic.
• Strong understanding of digital design for mixed-signal control loops.
• Experience designing digital backend logic for analog circuits such as ADCs or PLLs.
• Experience developing behavioral Verilog models including wreal constructs.
• Ability to write comprehensive RTL testbenches for functional verification.
• Strong understanding of design constraints and timing closure, particularly in mixed-signal designs.
• Experience handling multiple clock domains and clock gating.

Preferred Qualifications

• Basic understanding of SystemVerilog and assertions.
• Familiarity with signal processing concepts.
• Experience with MATLAB for modeling and algorithm validation.
• Exposure to mixed-signal verification methodologies.

About Us:

Silicon Patterns is a specialized engineering services company with deep expertise in pre-silicon and post-silicon design and verification. We deliver end-to-end semiconductor and embedded system solutions covering RTL Design, SystemC Modeling, Emulation, Design Verification (DV), Physical Design (PD), Design for Testability (DFT), and Pre- & Post-silicon Validation helping clients achieve faster, more reliable product development. Headquartered in Hyderabad, with offices in Bangalore and Raipur, and supported by our skilled engineering teams in Malaysia, we serve global clients through flexible engagement models like Time & Materials (T&M), Offshore Development Centers (ODC), Subcontracting, and Build-Operate-Transfer (BOT). Our expertise spans VLSI and Embedded Systems, with a strong focus on Wireless, IoT, and Automotive domains. We also work on advanced technologies including HBM3/3E workloads, AI/ML, GenAI/LLMs, and edge computing. At Silicon Patterns, were committed not only to technical excellence but also to maintaining a strong work-life balance for our teams because great engineering starts with well-supported people.

Website

https://www.siliconpatterns.com