Lead RTL Design Engineer

ACL Digital is Hiring for Lead RTL Design Engineers for Bangalore location

Experience : 7+Years

Skills Required:

• RTL design experience in RISC-V CPU Core Design involving CSRs, Load store,FPU (IEEE 754) IP, MMU, IO-MMU, Fetch, and Debug.
• Strong in ACE/CHI/AXI protocols & NoC architecture.
• Experience in Coherency Manager block RTL Modification and Performance related features.

Regards,

Sruthi

Mail Id: saisruthi.t@acldigital.com