Lead Physical Design Engineer

About Us:

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.

Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolves design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolves Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.

Tessolves clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit

Job Overview

Job Title: Physical Design Lead

Location: Bangalore

Experience: 8+ years in Physical Design

About the Role

We are looking for an experienced Physical Design Lead to join our team and drive end-to-end implementation of complex SoCs. The ideal candidate will have strong expertise in physical design flows, leadership skills, and the ability to mentor and guide a team of engineers.

Key Responsibilities

• Lead physical design activities for SoC/ASIC projects from RTL to GDSII.
• Drive floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure.
• Manage power, performance, and area (PPA) optimization.
• Handle physical verification (DRC/LVS) and sign-off processes.
• Collaborate with RTL, STA, and verification teams to ensure design quality.
• Provide technical leadership and mentor junior engineers.
• Interface with EDA vendors and resolve tool-related issues.

Required Skills

• Strong experience in physical design flows using tools like Cadence Innovus, Synopsys ICC2, or equivalent.
• Expertise in timing closure , power optimization , and signal integrity .
• Hands-on experience with floorplanning , CTS , and routing .
• Knowledge of low-power design techniques and DFT considerations.
• Familiarity with advanced nodes (7nm/5nm/3nm) is a plus.
• Excellent problem-solving and communication skills.

Qualifications

• Bachelors or Masters degree in Electrical/Electronics Engineering or related field.
• 8+ years of experience in Physical Design, with at least 2 years in a lead role.

Why Join Us?

• Opportunity to work on cutting-edge technologies.
• Collaborative and innovative work environment.
• Competitive compensation and benefits.

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