Lead PDK Runset Development Engineer

Job Title: PDK Runset Developer

Job Description:

We are seeking an experienced PDK Runset Developer to join our team and contribute to the development and optimization of physical verification rule decks for cutting-edge semiconductor technologies. The ideal candidate will have a strong background in EDA tools, DRC/LVS/PEX/PERC runset development, and a deep understanding of CMOS concepts. This role involves collaboration with cross-functional teams, ensuring the accuracy, efficiency, and scalability of runsets across advanced process nodes.

Responsibilities:

• Develop and maintain DRC/LVS/PEX/PERC runsets for advanced semiconductor process technologies.
• Debug, validate, and optimize rule decks for performance, scalability, and compatibility with various design environments.
• Collaborate with foundries to implement the latest process technology updates into runsets.
• Perform L0QA (Level 0 Quality Assurance) and ensure the accuracy of runsets through rigorous validation workflows.
• Design and enhance automated frameworks for continuous testing and validation of runsets.
• Provide technical support to internal design teams and external customers, resolving runset-related issues efficiently.
• Benchmark runsets across designs to ensure reliability, runtime efficiency, and compliance with process requirements.
• Work closely with EDA vendors to address tool-related challenges and implement optimized solutions.
• Stay abreast of emerging trends in semiconductor technologies and explore innovative approaches for physical verification.
• Create and update documentation and training materials for runset development, usage, and troubleshooting.

Qualifications:

• Education: B.Tech/M.Tech in Electronics, Electrical Engineering, or a related field.
• Experience:
• 10+ years of hands-on experience in runset development (DRC, LVS, PEX, PERC).
• Proven expertise in EDA tools such as Calibre, PVS, ICV, Pegasus, and Virtuoso.
• Skills:
• Proficient in scripting languages such as Unix Shell, Perl, Python, or TCL for automation and debugging.
• Strong understanding of Complex Design Rule , Ability to interpret rules from DRM and implement them with industry standard rule definition languages i.e. SVRF/ICVRL/PVL.
• Deep understanding of CMOS concepts, layout design, and physical verification flows.
• Experience with layout tools like Virtuoso, IC Workbench, Assura / Pegasus and Calibre nmDRC/nmLVS/DRV.
• Strong analytical and problem-solving skills.
• Excellent teamwork and collaboration abilities in dynamic environments.
• Effective communication skills to work with diverse teams and stakeholders.

Preferred Qualifications:

• Experience with technology nodes ranging from 180nm to 28nm.
• Knowledge of design for manufacturability (DFM) and yield enhancement techniques.
• Familiarity with AI/ML approaches in physical verification workflows.
• Exposure to design rule development and custom solutions for complex design requirements.