Lead Engineer

Role: Design for Test (DFT) About Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. Our success is anchored in the unparalleled expertise of our engineering leadership team, whose collective experience spans renowned technology giants like Google, Cisco, Microsoft, Oracle, Uber, Broadcom, and Sun. With a strong commitment to innovation and excellence, we deliver cutting-edge solutions that empower businesses to thrive in the ever-evolving digital landscape.

Experience: 5 25 Years

Locations: Bangalore / Hyderabad / Ahmedabad Job

Description: We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether you are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles that will challenge and grow your skills in advanced silicon testing. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, subsystem, and SOC designs. Core Responsibilities:

End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off.

Scan architecture definition and implementation at RTL and gate level, including EDT and OCC.

Execution of block-level ATPG, DRC analysis, and coverage optimization.

Handling of pattern simulations, including both timing and non-timing simulations.

SOC-level integration, including pattern retargeting to subsystem and full-chip levels.

Integration, simulation, and debug of MBIST, IJTAG, and Boundary Scan (JTAG).

Independent debugging of DFT simulations and netlist-related issues.

Close collaboration with design, verification, and physical design teams to ensure DFT readiness. Ownership of DFT sign-off activities and deliverables.

Key Responsibilities:

Develop and implement robust DFT architectures for IP, subsystem, and SOC designs.

Perform scan insertion, ATPG generation, and pattern validation at block and top levels.

Analyze and resolve coverage, DRC, and simulation failures to meet quality targets.

Define and execute DFT strategies aligned with project requirements and schedules.

Support pre-silicon and post-silicon test requirements.

Serve as the DFT point of contact for assigned projects, responsible for verification and test readiness sign-off. Technical Requirements: Must-Have Skills:

Strong experience in netlist handling and ATPG simulations.

Proven expertise in block-level and SOC-level pattern retargeting and debug.

In-depth understanding of ICL and PDL standards.

Hands-on experience with at least one major

DFT tool suite: o Siemens Tessent o Synopsys TestMAX / TetraMAX o Cadence Modus Preferred & Advanced Skills:

Experience with Streaming Scan Network (SSN).

Knowledge of Analog and Mixed-Signal DFT methodologies.

Proficiency with SpyGlass for DFT linting and early-stage analysis.

Exposure to RTL-level DFT insertion and validation.

Strong scripting skills (TCL, Python, Perl) for automation.

MBIST JD DFT MBIST Engineer Job Description Company: Eximietas Design Location: Bangalore / Hyderabad Experience: 4 10 Years Domain: VLSI / Semiconductor / SoC

About Eximietas Design Eximietas Design is a leading technology consulting and semiconductor solutions company, delivering end-to-end chip design and product engineering services across cutting-edge technologies. We specialize in full-chip ownership, advanced nodes, and complex SoC programs.

Role Overview We are looking for experienced DFT Engineers with strong MBIST expertise to join our growing team. The ideal candidate should have hands-on experience in memory test architecture, implementation, and SoC-level DFT integration.

Key Responsibilities Architect and implement MBIST solutions for SoC/Subsystem level Memory grouping, wrapper insertion, and BIST controller integration Debug and resolve MBIST-related issues at RTL and gate-level Perform DFT checks and ensure high test coverage Collaborate with Design, PD, and Verification teams for seamless integration Support silicon bring-up and post-silicon validation (if required)

Required Skills Strong hands-on experience in MBIST Good understanding of DFT concepts (Scan, ATPG, JTAG, IJTAG) Experience with industry-standard DFT tools (Mentor / Synopsys / Cadence/tessent) Knowledge of memory repair concepts and redundancy (added advantage) Exposure to LBIST is a plus Good debugging skills at RTL and netlist level

Eligibility 4 10 years of relevant DFT/MBIST experience Experience working on advanced technology nodes preferred Strong communication and collaboration skills