Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Please find the Verification JD

BE/BTECH/ME/MTECH

RESPONSIBILITIES:
- Develop test plans, tests, and verification infrastructure for complex IP’s/sub-system/SOC’s.
- Create verification environment using UVM methodology or equivalent.
- Build reusable bus functional models, monitors, checkers, and scoreboards.
- Drive verification closure through functional coverage.

SKILL SETS:
- BTech/ MTech in Engineering
- 7-8 years of VLSI industry experience in Verification.
- Strong experience in SoC level verification. Knowhow of IP/Subsystem experience
- Good experience in developing test bench/testbench components, testplans, test cases; developing functional coverage, assertions; coverage analysis.

- Strong in UVM, SV
- Experience in verification cycle for complex IP/SOC projects.
- Knowledge of protocols like UCIe, PCIe, DDR, USB, AMBA protocols preferred

- Strong individual contributor and a mentor with good debug and problem solving skills

We’re doing work that matters. Help us solve what others can’t.