IC Verification Engineer (ASIC)

The IC (ASIC) Verification Engineer is responsible for creating verification strategies for mixed-signal designs, including behavioural modelling of analog

circuits and using these models to enable comprehensive, top-down, metrics-driven validation of new analog and mixed-signal designs.

The IC Verification Engineer is also responsible for developing test benches and verifying integrated IP subsystems on the digital part of the IC.

IC (ASIC-) Verification will be done at the SOC level and block level.

This is a cross-functional role that requires close interaction with mixed-signal designers, systems and algorithm engineers, and others.

Experience: 3 to 12 Years

In this working area design, the IC (ASIC) verification engineer's tasks involve

• Develop functional models for Analog and/or Digital IPs
• Develop Digital- and Analog/Mixed-Mode Testbenches
• Interaction between IPs at chip level (analog and digital)
• Develop test benches.
• Functional verification
• Technical support of co-workers and IP designers
• Provide technical support to test engineers

IC Verification Engineer refers to ASIC, sensor, and other custom ICs.

The scope of activities of an IC Verification Engineer depends on the project type (COT, turn-key, ASSP,...).