Functional Verification Engineer

Job Title: Functional Verification Engineer

Location: Hyderabad

Role Summary

We are looking for an experienced Functional Verification Engineer with strong hands-on expertise in SystemVerilog/UVM . The ideal candidate will be proactive, self-driven, and capable of independently managing deliverables while working on block-level and IP-level verification.

Key Responsibilities

• Develop and maintain block-level testbenches using SystemVerilog/UVM.
• Create and execute verification plans (V-Plans) , run regressions, and drive coverage closure .
• Work on testbenches with Real Number Modelling (RNM) .
• Perform netlist and gate-level simulations (GLS) .

Technical Skills

• Strong hands-on coding experience in SystemVerilog/UVM .
• Proven experience in block/IP-level verification ; subsystem/SoC-level experience is an added advantage.

Strict Checklist (Must-Have Requirements)

Pure DV role with expertise in developing TB environments and components

GLS experience: 0-delay and timing simulations

Experience in integrating Real Number Models into the TB and running digital simulations

Strong experience in IP verification coverage closure (100% code + 100% functional coverage)

Typically expected in engineers with 6+ years of DV experience

Qualifications & Experience

• Education: Bachelors degree or higher in Electronics or related field.
• Experience: 510 years in Functional Verification.