FPGA Engineer – Spatial Vision Intelligence

We are building the next-generation AI chip for spatial vision intelligence , targeting humanoid robotics, XR platforms (including Meta XRclass systems), and neural-interfacelevel processors .

Our approach solves latency, thermal, and bandwidth limits at the chip level , not through software abstraction. By tightly coupling real-time vision, spatial understanding, and LLM-assisted intelligence , we deliver a user experience that is fundamentally impossible with software-only stacks.

This work is being executed with a world-leading semiconductor partner .

We are seeking a Lead FPGA / AI Chip Engineer who is deeply hands-on and capable of leading a small, high-profile core engineering team .

This role is for a builder: someone who writes RTL, debugs boards, closes timing, and ships silicon-proximate systemswhile setting technical direction through execution, not documentation.

You will lead implementation of the core spatial vision and intelligence pipelines , using FPGA as the execution platform and stepping stone toward production silicon.

Design, implement, and optimize FPGA-based pipelines for:

• Real-time image and sensor capture
• Spatial vision and contextual understanding
• AI pre-processing and on-device intelligence supporting LLMs
• Write and maintain production-quality RTL (Verilog / SystemVerilog / VHDL)
• Build deterministic, ultra-low-latency datapaths with tight power and thermal budgets
• Implement and tune memory and data movement (DDR, BRAM, DMA, streaming fabrics)
• Integrate high-speed I/O (MIPI CSI-2, PCIe, Ethernet, LVDS)
• Perform timing closure, power optimization, and hardware debugging
• Lead FPGA bring-up on real hardware (not simulations only)
• Work directly with AI, embedded, and semiconductor partner teams to align implementation
• Guide and review work of senior engineers while remaining personally accountable for delivery

• You will not be a pure architect detached from code
• You will not hand work off without ownership
• You will not optimize UX at the software layer alone

• 710+ years of hands-on FPGA engineering experience
• Strong mastery of RTL design and debugging in real systems
• Proven delivery of image / video / spatial processing pipelines on FPGA
• Deep understanding of latency, throughput, power, and thermal tradeoffs
• Experience with Xilinx (AMD) or Intel FPGA platforms and toolchains
• Comfortable leading a small elite team through example and code

• FPGA acceleration for AI / ML workloads (CNNs, transformers, pre/post processing)
• Edge AI systems coupled with LLM-based intelligence
• XR, humanoid robotics, or sensor-heavy embedded platforms
• Working alongside ASIC or custom silicon teams
• Performance- and thermally-constrained systems

• You will be part of the core execution team , not a support function
• Your code directly defines latency, heat, and intelligence capability
• You will help deliver a platform that sets a new baseline for spatial intelligence hardware

• Leadership of a high-profile, mission-critical engineering team
• Deep hands-on ownership of core chip-level technology
• Collaboration with a top-tier global semiconductor partner
• Competitive compensation with meaningful equity
• A chance to build technology that reshapes how machines perceive and reason