JOB Description.

Strong experience into FPGA Design
FPGA Design flow understanding , RTL coding, CDC, STA/Constraints, FPGA debug knowledge, logic design skills, high speed design, aware of very basic Zync design flow
Strong in SV & Verilog, etc.
Hands on experience in RTL coding, Spyglass, Lint, design knowledge, STA, etc....
Added advantages if they worked telecommunication domain (5G, Radio Subsystems, AMS etc.), any Scripting Knowledge
Added advantages if they know APB, AHB, AXI, Ethernet, PCIe etc...
Knowledge in debugging using inbuilt logic analyzers
Expertise in setting up and using tools like Intel, Xilinx/AMD FPGA tools
Added Advantages if they know Agile way of working.
Good Communication Skills

Good Knowledge in RTL FPGA design using Verilog/System Verilog

Good Knowledge in FPGA device architecture
Good knowledge in FPGA clock structure
Good Knowledge in RTL quality checks (Lint, CDC,RDC)
Good Knowledge of synthesis , Place and Route and STA
Good understanding of bus protocols (AXI, AvMM, AHB)
Good Knowledge of slow speed protocols : I2C, SPI, UART MDIO etc..
Good Knowledge in PCIe IP usage
Good knowledge in error detection and correction
Knowledge in constraints
Knowledge in debugging using inbuilt logic analyzers
Knowledge in FPGA tools like : Lattice Radiant (Must). Intel, Xilinx/AMD FPGA tools
Basic Understanding of scripting languages like Make flow, Perl, shell, python etc
Able to review design documents for FPGA validation team
Knowledge in Agile Methodology, GIT

FPGA Design