FORMAL PROPERTY VERIFICATION

• Conduct comprehensive formal verification of hardware designs and digital systems, ensuring all properties and specifications are met.
• Collaborate with design and development teams to define formal properties and verification requirements.
• Prepare and execute verification test plans, analyze results, and document findings for internal and external stakeholders.
• Identify, troubleshoot, and resolve verification issues, providing technical guidance and support throughout the project lifecycle.
• Maintain up-to-date expertise on formal verification methodologies and tools, advocating best practices within the team.
• Contribute to process improvement initiatives to enhance the efficiency and effectiveness of the verification cycle.

Skill Requirements

• Minimum of 4 years of professional experience in formal property verification or related hardware verification domains.
• Strong technical background in digital design, verification methodologies, and EDA tools (e.g., JasperGold, Questa Formal, etc.).
• Bachelors or Masters degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• Proficiency in hardware description languages (HDL), such as Verilog, VHDL, or SystemVerilog.
• Solid understanding of formal verification techniques, algorithms, and industry standards.
• Excellent problem-solving skills and attention to detail.
• Effective communication and interpersonal skills for cross-functional collaboration.