Field-Programmable Gate Arrays Engineer

Overview We are seeking an FPGA Engineer with strong expertise in high-speed serial protocol-based designs. The ideal candidate is smart, energetic, and hands-on, with proven experience in high-speed FPGA development and the ability to solve complex design challenges. Preferred protocols: PCIe, NVMe, and CXL. Other valuable experience: Ethernet (10G/25G/100G), USB 3.x/USB4, SATA, SAS, InfiniBand, DisplayPort, HDMI, MIPI M-PHY.

Responsibilities Design, architect, and develop FPGA RTL (VHDL/Verilog) logic and subsystems for highspeed serial protocols. Address FPGA design challenges such as CDC, multi-clock domains, timing closure, and SerDes-related issues. Drive timing closure and optimization using FPGA synthesis and implementation tools (Xilinx Vivado). Debug and validate FPGA and board-level issues, ensuring robust high-speed interface performance. Collaborate with global R&D teams to deliver production-ready FPGA solutions. Leverage AI-assisted tools (e.g., GitHub Copilot, LLM-based aids) to accelerate RTL development and productivity.

Requirements 7+ years of FPGA design and development experience. Strong expertise in high-speed serial protocols (PCIe, NVMe, CXL preferred; others such as Ethernet, USB 3.x/USB4, SATA, SAS, InfiniBand, DisplayPort, HDMI, or MIPI M-PHY also acceptable). Proven skills in high-speed FPGA design, including CDC handling, timing closure, and interface validation. Hands-on experience with FPGA synthesis/implementation tools (Xilinx Vivado: synthesis, place-and-route, timing closure, on-board debug). Experience with FPGA simulation tools (ModelSim, Que