Field-Programmable Gate Arrays Engineer

Hi All,

We HCL Technologies looking for, FPGA Design Engineer.

Detailed Responsibilities

• Develop, implement, and verify FPGA RTL designs in accordance with project requirements.
• Conduct Lint Check and Clock Domain Crossing (CDC) analysis to ensure design integrity and reliability.
• Apply timing concepts to optimize and validate FPGA designs for performance and accuracy.
• Perform IP integration, ensuring seamless functionality within complex system architectures.
• Collaborate with hardware and software teams to troubleshoot, debug, and resolve issues on FPGA boards.
• Lead or participate in protocol analysis and implementation, ensuring compliance with industry standards.
• Document design processes, test plans, and results to support project deliverables and knowledge sharing.
• Engage in continuous improvement initiatives to enhance design quality, efficiency, and innovation.

Skill Requirements

• Bachelors or Masters degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Minimum 6 years of experience in FPGA RTL design, with hands-on expertise in Lint Check and CDC analysis.
• Strong understanding of timing concepts and their application in FPGA development.
• Proven track record in RTL design or IP integration for at least 6 years.
• Experience with FPGA protocols and debugging skills on FPGA boards.
• Proficiency in hardware description languages such as Verilog and VHDL.
• Familiarity with FPGA development tools and methodologies.
• Excellent problem-solving, communication, and teamwork skills.