Field-Programmable Gate Arrays Engineer
ACL Digital
1 - 2 years
Hyderabad
Posted: 12/12/2025
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Job Description
RTL-FPGA Engineer
Location : Hyderabad
Experience : 1-2 years
understanding of Vivado Flow and HW validation using Xilinx(AMD) FPGAs.
Strong understanding of FPGA flow using Vivado, Logic design, Digital design etc.
. Expertise RTL Coding in Verilog / System Verilog or VHDL
. Knowledge in Xilinx FPGA architecture
Good Knowledge in Tcl or Python scripting
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