Field-Programmable Gate Arrays Engineer

RTL-FPGA Engineer

Location : Hyderabad

Experience : 1-2 years

understanding of Vivado Flow and HW validation using Xilinx(AMD) FPGAs.

Strong understanding of FPGA flow using Vivado, Logic design, Digital design etc.

. Expertise RTL Coding in Verilog / System Verilog or VHDL

. Knowledge in Xilinx FPGA architecture

Good Knowledge in Tcl or Python scripting