Ethernet / RDMA Verification Engineer

Hyderabad

Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore

Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market

Ethernet / RDMA Verification Engineer

Experience: 10+ Years

Location : Hyderabad

Role Overview

We are seeking a highly experienced Design Verification professional with 10+ years of industry experience in SoC and subsystem-level verification. The candidate will play a key role in architecting, developing, and executing comprehensive verification strategies for complex, high-performance IPs and subsystems.

The ideal candidate should possess strong expertise in PCIe and Ethernet/RDMA-based systems, along with a deep understanding of DMA architectures, memory subsystems, and advanced system-level concepts. This role requires close collaboration with RTL, architecture, firmware, and system teams to ensure functional correctness, performance validation, and successful tape-out.

Key Responsibilities

• Lead end-to-end verification of complex SoC subsystems and high-speed IP blocks
• Define verification strategy, methodology, coverage models, and sign-off criteria
• Develop scalable SystemVerilog/UVM-based verification environments from scratch
• Drive block-level, subsystem-level, and full-chip verification
• Debug complex protocol, architectural, and integration issues
• Perform performance validation including latency, throughput, and stress scenarios
• Work closely with RTL, architecture, firmware, and post-silicon teams
• Contribute to verification closure including functional, code, and assertion coverage

Required Technical Expertise

Strong Experience In:

• PCIe (Gen4/Gen5 or higher) verification
• Ethernet (10G/25G/100G or higher) and RDMA (RoCE/iWARP) verification
• DMA engines and memory subsystem architectures
• Integration and validation of high-speed interconnect-based designs

Deep Understanding Of:

• Virtual memory systems including IOMMU/GMMU architectures
• Memory ordering rules and consistency models
• Queue-based execution engines and descriptor-based architectures
• Data movement architectures and buffer management schemes

Experience With:

• High-performance NICs and RDMA subsystems
• System-level integration and stress testing
• Performance tuning and bottleneck analysis
• Debugging complex transaction-level and data-path issues

Core Verification Skills

• Strong proficiency in SystemVerilog and UVM
• Solid understanding of Object-Oriented Programming concepts
• Experience in building reusable, modular verification environments
• Expertise in writing assertions, checkers, scoreboards, and coverage models
• Familiarity with scripting languages such as Python, Perl, or Tcl
• Experience with industry-standard simulation and debug tools

Contact: Uday

Mulya Technologies

Email: muday_bhaskar@yahoo.com