DFT Engineer

About the Role

As a DFT Engineer, you will be a key player in ensuring the reliability and manufacturability of our next-generation silicon. In 2026, the complexity of AI-driven chips requires advanced testability solutions. You will own the DFT flow from architecture to sign-off, focusing on maximizing coverage while minimizing test time.

Responsibilities

• Architecture & Insertion: Design and implement Scan Architectures, including hierarchical scan and scan compression.
• ATPG: Generate and validate high-quality test patterns for Stuck-at, Transition, and Path Delay faults.
• Self-Test Mastery: Integrate and verify MBIST (with Memory Repair/BISR) and LBIST for complex logic blocks.
• Standard Compliance: Implement JTAG (IEEE 1149.1/6) and IEEE 1500 core wrappers.
• Automation: Develop and maintain automation scripts using TCL, Perl, or Python to streamline the DFT flow.
• Validation: Support silicon bring-up and debug using SIMS and ATE data.

Qualifications

• Experience: 3 to 6 years of hands-on experience in DFT.
• Tools: Proficiency in industry-standard tools (e.g., Synopsys TestMAX, Siemens Tessent, or Cadence Modus).
• Scan insertion, ATPG (Stuck-at, Transition, Path Delay), JTAG, SIMS, MBIST, LBIST, and scripting (Perl/TCL/Python)
• Join Date: Immediate to 30 days preferred.

Required Skills

• Hands-on experience in DFT.
• Proficiency in industry-standard tools.

Preferred Skills

• Experience with advanced testability solutions.

Location: Bangalore / Employment Type: Full-Time