Senior DFT engineer preferably with 10+ yrs experience in SoC DFT implementation and verification of scan architectures, JTAG, boundary scan, memory BIST, ATPG and LBIST.
BE/ME/B.Tech/M.Tech from reputed institutes with relevant industry experience
The engineer should be well versed in Verilog/VHDL RTL coding, automation, experienced in using Mentor DFT tool sets and reasonable acquaintance with Synopsyss scan insertion and timing analysis tools along with standard linting tools.
The engineer needs to have hands-on experience in scan insertion, JTAG, LBIST, ATPG DRC and coverage analysis, Simulation debug with timing/SDF and post silicon debug.
Must have worked on more than one SoC , from start to end.
Must be proactive, collaborative, self driven and detail-oriented capable of exercising independent judgment
The engineer with experience on debug and root cause the problem in simulation failures and silicon
Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills
Show an engaged curiosity, a will to understand the mechanisms behind the effects, an eagerness to constantly learn and improve

DFT Engineer