We are having opportunities for DFT Engineers

Role: DFT Engineer

Exp: 5+ yrs

Loc: BLR

NP: Immediate to 15 days

JD:

Good exposer of complete DFT Cycles and able to work and debug independently
Very good experience on MBIST implementation, verification & debug with and without timing simulation.
Have sound knowledge of DFT STA and constraints support for timing closer team.
Should have good experience on ATPG pattern generation, simulation and sound debug capabilities
Good to have knowledge of BSCAN and debug capabilities of failing patterns.

Role: DFT Lead

Exp:8+yrs

Loc: BLR

NP: Immediate to 15 days

JD:

Should have at least 8+ years of experience in DFT domain, have experience with JTAG, scan insertion, compression, ATPG, boundary scan
Should be aware of IC level DFT architecture
Should have experience with timing & notiming simulations, memory bist (RAM & ROM).
Should be able to work independently and be a team player
Post silicon debug experience is a plus
Experience with Verilog/VHDL, Synthesis, STA, LEC a plus, Ultra Low Power Designs , Conformal Low power is a plus.
Analog DFT experience is a plus.

If Interested, please share your profile to my mail id

DFT Engineer