DFT engineer

SR DFT engineer/ Leads

Exp- 4 years+

DFT Tools flow: Mentor Tessent

Implementation: More RTL level implementation

LEC at RTL level (pre-DFT vs post-DFT) and gate level

SoC/Block : SoC as well as Subsystem/block/partition level

Good to have : SSN is must

Insertion: Scan, MBIST, occ, edt using ARM DFT flow

Patten generation, retargeting and simulation at block as well as SOC.

Simulation: zero delay or timings simulation with using sdf

Coverage closure

Scan Synthesis and timing constraints creation.