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DFT Engineer

Best NanoTech

2 - 5 years

Bengaluru

Posted: 10/01/2026

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Job Description

Job Description

  • Develop and implement DFT architecture for complex SoCs and IPs.
  • Perform Scan Insertion, Scan Stitching, and Scan Chain Optimization.
  • Execute ATPG pattern generation, compression, coverage analysis, and pattern debug.
  • Implement and validate MBIST/BIST architectures, including memory test algorithms and integration.
  • Work closely with RTL, PD, and Verification teams to ensure DFT features are seamlessly integrated.
  • Perform DFT rule checks, linting, and resolve violations.
  • Conduct gate-level simulations for DFT verification (DFT-GLS).
  • Support timing closure for DFT modes in collaboration with STA teams.
  • Generate high-quality test patterns for production test and support bring-up teams during silicon validation.

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