We are seeking an experienced DFT Engineer to join our ASIC/SoC design team. The

candidate will be responsible for planning, implementing, and validating Design-for-Test

strategies to ensure optimal testability and quality of semiconductor designs.

Key Responsibilities:

Design, implement, and verify DFT methodologies including Scan Insertion,

MBIST, LBIST, and ATPG.

Perform fault simulation and test coverage analysis to ensure design robustness.

Collaborate with RTL, Physical Design, and Verification teams for seamless DFT

integration.

Develop and maintain automation scripts using Python, Perl, or TCL.

Analyze and debug DFT-related issues during design and post-silicon phases.

Support tape-out readiness and post-silicon test planning.

Required Skills & Expertise:

Strong knowledge of DFT methodologies (Scan, MBIST, LBIST, ATPG).

Hands-on experience with DFT tools such as Mentor Tessent, Synopsys DFTMAX,

or equivalent.

Proficiency in scripting languages (Python, Perl, TCL) for automation.

Understanding of ASIC/SoC design flow and digital verification principles.

Excellent problem-solving and analytical skills.

Qualifications:

Bachelors or Masters degree in Electronics, VLSI, or related field.

5+ years of experience in DFT for ASIC/SoC projects.

Why Join Us:

Work on cutting-edge semiconductor designs in a collaborative environment.

Exposure to end-to-end DFT flows and automation strategies.

Opportunity to grow within a fast-paced, innovative company.

DFT Engineer