DFT (Design-For-Testability) Engineer

Position Summary:

DFT (Design-For-Testability) Engineer

Experience: 1015 Years

Location: Bangalore

About the Role:

We are seeking an experienced DFT Engineer to join our ASIC/SoC design team. You will be responsible for developing DFT architectures, integrating test logic, enabling high fault coverage, and supporting silicon bring-up to ensure robust manufacturability and yield.

Key Responsibilities:

Develop and implement DFT strategies: scan insertion, ATPG, BIST, boundary scan, JTAG.

Work closely with RTL, verification, physical design, and layout teams to integrate test features with minimal area/performance impact.

Build test plans, test infrastructures, and test patterns; perform automated test generation, fault coverage analysis, and debug test issues.

Support silicon bring-up, analyze test results, and drive design improvements for yield and reliability.

Perform DFT/DFM analysis and ensure compliance with manufacturing constraints.

Maintain documentation for DFT architecture, flows, scripts, and mentor junior engineers where required.

Required Qualifications:

Bachelors or Masters degree in Electrical/Electronics/Computer Engineering or related field.

515 years of experience in DFT / ASIC / SoC test design & infrastructure roles.

Strong understanding of digital design, RTL, and SoC design flows.

Hands-on expertise with DFT methodologies/tools: scan insertion, BIST, ATPG, boundary scan, JTAG, and industry EDA tools.

Proficiency in Verilog/SystemVerilog and scripting languages (Python/Perl/TCL).

Excellent debug, analytical, and problem-solving skills.

General Expectations:

Strong communication and cross-functional collaboration skills.

Ability to work in a fast-paced environment and deliver on tight timelines.

Self-starter with a track record across multiple tape-outs or silicon bring-ups.

Preferred: experience in automotive, data center, storage, multimedia, or communication domains.