DFT Architecture

Processor team is focused on developing a family of MCUs that enable a wide range of Industrial and Automotive applications.

As a DFT engineer in the team, you will be working independently of DFT implementation, verification and supporting post silicon debug for the multiple Simplelink Connectivity SoCs.

What you will be doing

Responsible for DFT pattern generation, simulations and debug (including setup creations, any required automation, etc.)

Also responsible for the cross functional issues and dependencies across RTL integration, synthesis, constraints, timing analysis and related analysis and debugs

Overcome the different design and IP challenges to enable achieving all the structural coverage goals

Drive new techniques and methodologies to enable test time and test cost reduction for the SoCs

SoC DFT verification in RTL and GLS

Responsible for driving the requirements with all the stakeholders

You should have:

• 5-10 years experience
• Experience of working on chip level DFT
• Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification
• Must have experience generating scan patterns and coverage statistics for various fault models like stuck at (Nominal and VBOX), IDDQ, Transition faults
• Experience with gate level pattern simulations and debug
• Exposure to debugging tester failures of scan patterns, diagnosis and pattern re-generation
• Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc)
• Good understanding of constraints development for Physical Design implementation / Static Timing Analysis

Exposure to post silicon debug is a plus

Excellent debugging and problem solving skills

Effective communication skills to interact with all stakeholders

Must be highly focused and remain committed to obtaining closure on project goals

Basic requirements:

• 5-10 years of experience in SoC DFT
• Bachelor or Masters degree in Electrical engineering
• Experience with ATPG tools
• Experience with simulations and pattern debug