DFT

Job Title: DFT Engineer / Senior DFT Engineer / Lead / Manager / Staff Engineer

Experience Range: 3 17 Years

Location: Bangalore / Chennai

Notice Period: Immediate to 90 Days

Open Positions:

• Lead / Manager 4 Positions
• Junior & Mid-Level 20 Positions
• (For multiple Customer-Based, In-House & Turnkey Projects )

Send Profiles to:

About the Role

We are hiring passionate Design-for-Test (DFT) professionals to work on next-generation semiconductor SoCs, cutting-edge nodes, and high-volume production silicon. The role involves ownership of DFT architecture, implementation, signoff, silicon bring-up, and test quality optimization. Opportunities available across Automotive, AI/ML, Networking, 5G, Storage, Consumer & High-performance Computing domains.

Key Responsibilities

Depending on experience level (Junior/Mid/Lead/Manager/Staff):

• Ownership of DFT architecture, planning, integration & verification
• Development of Scan/ATPG/MBIST/JTAG/BSCAN/Boundary Scan logic and flows
• DFT insertion, pattern generation, fault coverage analysis and sign-off
• Work with RTL, Physical Design, STA, and Silicon Validation teams
• ATPG coverage improvements, debugging and yield enhancement
• Memory BIST architecture and test algorithm integration
• Post-silicon bring-up, ATE vector debug, production ramp support
• Drive DFT methodologies, automation & best practices across projects
• Mentoring juniors, project planning & customer interaction (Lead/Manager roles)

Mandatory Technical Skills

Candidates should have experience in one or more DFT areas:

Scan Insertion, Compression & ATPG

JTAG/BSCAN/Boundary Scan/IEEE 1149.x

MBIST/Logic BIST/Analog & Mixed-Signal BIST

ATPG pattern debugging, DRC/Lint fixing, STA timing for test modes

DFT Sign-off & Coverage closure

Tool Experience (preferred):

Siemens Tessent , Synopsys TetraMAX , D-Compiler , Modus , Genus , SMS , FastScan , TestMAX , Shell scripting , Python/TCL for automation

Nice to Have / Emerging & Future DFT Technologies

(To attract advanced profiles & future-ready talent)

DFT for 2.5D/3D-IC & Chiplets (UCIe/OpenHBI testing frameworks)

AI-Driven ATPG optimization & test time reduction

DFT for RISC-V Architectures, Automotive ASIL standards

Logic-Diagnosis, Scan-Compression Innovations

LBIST for functional safety / ISO26262 compliance

Design-for-Security (DFSec) Secure JTAG, PUF, Anti-tamper DFT

Silicon lifecycle management, Telemetry-based test analytics

Yield ramp modeling & ML-based failure prediction

Who Should Apply?

We are looking for engineers who:

• Have strong fundamentals in digital/ASIC/SoC design & test
• Are passionate about innovation in DFT , automation & scalable methodologies
• Enjoy solving complex silicon challenges across latest technology nodes
• Can work in a fast-paced environment with global customers

Perks & Career Growth

• Work on advanced nodes (7nm 3nm 2nm) and cutting-edge SoCs
• Opportunity to contribute to future-ready DFT workflows & R&D initiatives
• Leadership & customer-facing roles for high performers
• Exposure to In-House, Turnkey & Global Tier-1 Semiconductor projects

If you are eager to shape the next era of silicon , drop your resume at: