Design Verification Lead

Senior IP/SoC Design Verification Engineers (8+ yrs)

Locations: Bangalore | Chennai | Hyderabad | Noida

Company: Tessolve Semiconductor

Looking for experienced DV engineers with strong SystemVerilog + UVM skills and hands-on expertise in high-speed interfaces like DDR, PCIe, USB, Ethernet, SerDes, NVMe, UCIe.

Must Have:

8+ years in IP/Subsystem/SoC DV

UVM TB development, SVA, coverage, debugging

Experience with VCS/Questa/Xcelium, Verdi/DVE

Scripting (Python/Perl/Shell)

Apply:

Subject: Senior DV Engineer Preferred Location