Design Verification Engineer

Digital Verification Engineer-

Looking for Digital verification engineers with 3-10 years of experience with Block-level and Chip-level verification using System Verilog UVM environment. It would be preferrable to have engineers with hands-on experience with DSP and/or PLL products (but this is not mandatory).

Responsibilities

·       Define and implement self-checking test cases based on functional requirements.

·       Contribute to our ever-evolving verification infrastructure components.

·       Triage of regressions, debug of RTL and Gate level simulations, analysis of coverage, and working with other teams to resolve issues and achieve verification closure.

·       Work with diverse design and verification team members, local and remote
 

Basic Qualifications

·       Understanding standard specifications/ functional specifications/ feature enhancements for the product to create and execute detailed verification plans.

·       Knowledge of System Verilog and UVM environments for digital verification

·       Experience with Synopsys and/or Cadence simulation tools

·       Experience with System Verilog assertions, functional coverage, and code coverage 

·       Fast learner with the ability to work under minimal supervision.

·       Effective team player with good communication skills