Design Verification Engineer

Were hiring a SoC Verification Engineer with real hands-on muscle.

If youve spent 5+ years building and breaking complex SoC/IP subsystems, live in System Verilog/UVM, and can drive constrained-random verification like second nature, youll feel right at home.

Responsibility

• Youll craft solid testbenches, nail coverage closure, debug without blinking, and handle protocols like AXI, AHB, APB, PCIe with ease. VCS, Questa, Xcelium, Verdi, Jenkins, Git, Python/TCLif these are your everyday tools, lets talk.
• If your CV shows UVM, SVA, functional coverage, strong scripting, and solid protocol depth, drop me a note.