Design Verification Engineer

Position: ASIC Design Verification Engineer

Location: Hyderabad

Experience: 35 Years

Hiring Design Verification Engineer with strong IP-level / Functional Verification experience using UVM to support high-quality IP development programs. If you enjoy solving real-world verification problems and contributing to high-quality IP delivery, this role offers an excellent opportunity to grow and make an impact.

Job Description:

• Hands-on experience in IP-level functional verification using SystemVerilog and UVM, including testbench development and test case creation.
• Perform RTL verification, debug functional issues, analyze waveforms/logs, and ensure quality IP delivery within project timelines.
• Solid understanding of digital design fundamentals and industry-standard verification methodologies.
• Exposure to on-chip bus and interface protocols such as AXI, AHB, and Ethernet for IP verification.
• Utilize scripting languages (Python, Perl, Shell) to support verification automation, regression, and productivity improvements.

Thanks,

Karthik Kumar