Design Verification Engineer

Responsibilities

As one of important team member of wireless connectivity group, you will

1 Perform digital verification for SoC subsystems and IP to ensure compliance with specifications

2 Develop verification plans, write test cases, and ensure coverage for functionality, performance, and low-power scenarios

3 Build and maintain verification environments using System Verilog/UVM methodology

4 Run simulations, debug issues, analyze waveforms, and identify root causes

5 Collaborate closely with design, architecture, and algorithm teams to resolve issues efficiently

6 Contribute to improving verification flows and enhancing overall quality and productivity

Requirements

1 masters degree in electronic engineering or computer engineering 5+ years

2 Solid understanding of digital design and verification flow, with knowledge of SoC architecture

3 Proficient in System Verilog and familiar with UVM methodology

4 Hands-on experiences with RTL simulation and debugging using tools like VCS and Verdi

5 Familiar with EDA tools and scripting languages (Python/Perl) for verification automation

6 Understanding of Bluetooth protocol and prior experience in related verification is highly desirable

7 Strong communication and teamwork skills