Design Verification Engineer

Design Verification | 5 To 16 years | Bangalore

Responsibilities:

• Perform IP/SoC DV and CPU DV for complex architectures.
• Develop scalable test benches (BFM, Scoreboard, Checkers, Monitors) in SystemVerilog and UVM.
• Create tests, functional coverage models, and SystemVerilog assertions.
• Debug issues related to memory architecture (DRAM, Cache, MMU), AXI, PCIe, DDR/HBM.
• Collaborate with design teams to ensure verification completeness.

Technical Skills:

• Excellent in System Verilog (SV) and UVM.
• Strong knowledge of AMBA protocols, ARM v8/v9, RISC-V, x86 architecture.
• Proficient in OOP/C++, Python scripting.
• Excellent debugging skills.