Design Verification Engineer

Job Title: DV Engineer IP / SoC

Location: Noida / Bangalore

Notice Period: Immediate 15 Days

Experience: 35 Years

About the Role

We are looking for a skilled Design Verification (DV) Engineer with hands-on experience in IP and SoC level verification . The ideal candidate should have a strong understanding of digital design concepts, verification methodologies, and industry-standard tools used in semiconductor verification.

Key Responsibilities

• Work on IP and SoC level verification using industry-standard methodologies.
• Develop, maintain and execute verification test plans and environments.
• Debug failures, analyze root causes, and collaborate with design and architecture teams for closure.
• Run simulations, analyze results, and achieve coverage closure for assigned blocks and SoC features.
• Participate in feature integration, regressions, and validation cycles across the verification workflow.

Required Skills & Expertise

Strong knowledge of digital design with IP / SoC level verification

Experience in HVL such as SystemVerilog, UVM/OVM/SystemC

Experience in HDL such as Verilog

Knowledge of ARM/DSP CPU architecture

Familiarity with High-Speed Peripherals: USB2/3, PCIe, Audio/Multimedia

Experience with Power-aware Verification, GLS, Test Vector Generation

Exposure to version control tools like ClearCase / Perforce

Scripting experience in Perl, TCL or Python

Regards

Anil Sheoran