Design Verification Engineer

Job Role: DV Engineer

Experience: 4-8 years of experience

Job Description

• Strong Experience in IP/Sub System verification
• Strong working knowledge of any one protocol Ethernet, MIPI, WIFI, PCIe, CXL, DDR, AMBA: AXI, AHB, NOC
• Excellent in System Verilog (SV), Universal Verification Methodology (UVM), test bench component development (BFM, Scoreboard, Checkers, Monitors), assertions, testbenches, test plans, and coverage & assertions
• Excellent debugging skills