Design Verification Engineer
ACL Digital
2 - 5 years
Hyderabad
Posted: 08/01/2026
Getting a referral is 5x more effective than applying directly
Job Description
#ACL Digital is Hiring: GPM Subsystem Verification Engineer
Must-have: UVM, System Verilog, IP Verification
Preferred: Power Management IP, Firmware DV, Python/Perl
Full-cycle DV: test plan tape out
Collaborate with top DV, design & architecture teams
Apply/Refer:
#ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog
#PowerManagementIP #HyderabadJobs #VLSICareers
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