Design Verification Engineer
ACL Digital
2 - 5 years
Hyderabad
Posted: 12/02/2026
Getting a referral is 5x more effective than applying directly
Job Description
#ACL Digital is Hiring: GPM Subsystem Verification Engineer
Must-have: UVM, System Verilog, IP Verification
Preferred: Power Management IP, Firmware DV, Python/Perl
Full-cycle DV: test plan tape out
Collaborate with top DV, design & architecture teams
Apply/Refer: himabindu.jeevarathnam@acldigital.com
#ACLDigital #HiringNow #DesignVerification #UVM #SystemVerilog
#PowerManagementIP #HyderabadJobs #VLSICareers
Services you might be interested in
Improve Your Resume Today
Boost your chances with professional resume services!
Get expert-reviewed, ATS-optimized resumes tailored for your experience level. Start your journey now.
