Design Verification Engineer

Role: Design Verification Engineer

Exp : 3 to 5years

Location : Chennai

Preference : Immediate to 30days notice & available to F2F interview in Chennai

• Strong knowledge of digital design with IP/ SoC level verification
• Experience in HVL such as System Verilog, UVM/OVM/ System C
• Experience in HDL such as Verilog
• Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia
• Familiarity with Power-aware Verification, GLS, Test vector generation
• Exposure to Version managers like Clearcase/perforce
• Scripting language like Perl, Tcl or Python