Design Verification Engineer
ACL Digital
5 - 15 years
Bengaluru
Posted: 06/03/2026
Job Description
Hello from ACL Digital!
Experience: - 5 - 15 years
JD 1: Design Verification Lead RISC-V | Location: Bangalore | Notice: Immediate
We are seeking a DV Lead with strong RISC-V core/SoC verification experience and hands-on expertise in SystemVerilog, UVM, and SVA.
Lead end-to-end verification including test plan creation, coverage closure, assertions, and complex RTL debugging.
Drive IP/subsystem integration and SoC-level verification while mentoring a small verification team.
Experience with AXI/AHB, scripting (Python/Shell), and tools like VCS/Xcelium/Questa is required.
Strong ownership mindset with ability to review architecture and ensure quality signoff.
If youre not interested, please refer a suitable candidate.
Contact: 8754387484
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