Design Verification Engineer

Design Verification Lead / Senior DV Engineer

Experience: 4 20 Years

Location: Bangalore

Notice Period: Immediate to 30 Days or serving notice period

Job Description:

We are looking for experienced Design Verification (DV) Engineers and Leads with strong SoC verification expertise and hands-on technical skills.

Key Responsibilities:

• Lead end-to-end SoC/IP verification activities
• Develop detailed test plans and verification strategies
• Build and maintain UVM-based testbenches using SystemVerilog
• Knowledge of protocols (AXI/AHB/APB/PCIe/USB/DDR etc.) is a plus

Good to Have:

• Experience in low power verification (UPF)
• Experience with formal verification
• Exposure of RISC-V

Interested candidates or references can share resumes to:

kalavathi.srinivas@acldigital.com