Design Verification Engineer

Job Role : Design Verification Engineer (Low power)

Experience: 8+ years

Location : Bangalore / Hyderabad

Responsibilities

Execute power-aware simulations and debug failures related to power intent

Integrate UPF with UVM testbenches and VIPs

Create directed and constrained-random tests for low-power scenarios

Verify: Power gating, Isolation, Retention save/restore & Reset behavior across power domains

Develop assertions and functional coverage for power states and transitions

Support power-aware regression and sign-off

Collaborating with RTL, power architects

Requirements

Strong hands-on experience with SystemVerilog & UVM

Solid understanding of UPF / power intent modeling

Experience with power-aware simulation

Knowledge of: Power domains & power states, Isolation, retention, level shifters, Reset vs power interactions

Strong debug skills across RTL, UPF, and testbench