DESIGN FOR TESTABILITY
LeadSoc Technologies Pvt Ltd
2 - 5 years
Bengaluru
Posted: 31/01/2026
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Job Description
Leadsoc is hiring !!
Experience: 5 to 12 years
Notice Period: Immediate to 30 days
- Hands-on experience in Tessent DFT RTL insertion, DRC checks and debug is a must.
- Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation.
- Working knowledge of timing enabled GLS and related debug.
- A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST controllers, IJTAG, IEEE 1600 standard, and Boundary scan.
- Should be able to handle tasks independently.
- The candidate needs to have good debug skills and should be able to communicate related issues to the larger team.
- Working knowledge of TCL is an add-on.
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