DESIGN FOR TESTABILITY

Leadsoc is hiring !!

Experience: 5 to 12 years

Notice Period: Immediate to 30 days

• Hands-on experience in Tessent DFT RTL insertion, DRC checks and debug is a must.
• Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation.
• Working knowledge of timing enabled GLS and related debug.
• A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST controllers, IJTAG, IEEE 1600 standard, and Boundary scan.
• Should be able to handle tasks independently.
• The candidate needs to have good debug skills and should be able to communicate related issues to the larger team.
• Working knowledge of TCL is an add-on.

Please share your profile for jhansi.bv@leadsoc.com for further discussion