Design Engineer I

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role : Design Engineer 1, Digital Physical Desing

• Responsibilities
  • Block level Netlist to GDS delivery
  • Subsystem level PnR and timing closure
• Required Skills
  • 3+ years of experience in PnR and STA
  • Handson experience in RTL/Netlist to GDS delivery of blocks
  • Good exposure to Placement, CTS and Routing techniques
  • Capable of doing PV and IREM fixes along with timing
  • Good exposure to Cadence EDA tool set needed for PD
  • TCL and PERL scripting knowledge and experience in writing the scripts
• Optional Skills
  • Complex blocks floorplan, PnR and STA
  • Complex IP integration like DDR and PCIe
  • Hands on experience in low power designs
  • Good understanding of DFT stitching
  • Exposure to any of 7/6nm, 5/4nm & 3/2nm technologies

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